Description
Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect TSC when Secure TSC is enabled potentially resulting in a loss of guest integrity.
Scores
CVSS v3
4.9
EPSS
0.0005
EPSS Percentile
13.9%
Attack Vector
NETWORK
CVSS:3.1/AV:N/AC:L/PR:H/UI:N/S:U/C:N/I:H/A:N
CISA SSVC
Vulnrichment
Exploitation
none
Automatable
no
Technical Impact
partial
Details
CWE
CWE-682
Status
published
Products (50)
amd/epyc_7203_firmware
< milanpi_1.0.0.c
amd/epyc_7203p_firmware
< milanpi_1.0.0.c
amd/epyc_72f3_firmware
< milanpi_1.0.0.c
amd/epyc_7303_firmware
< milanpi_1.0.0.c
amd/epyc_7303p_firmware
< milanpi_1.0.0.c
amd/epyc_7313_firmware
< milanpi_1.0.0.c
amd/epyc_7313p_firmware
< milanpi_1.0.0.c
amd/epyc_7343_firmware
< milanpi_1.0.0.c
amd/epyc_7373x_firmware
< milanpi_1.0.0.c
amd/epyc_73f3_firmware
< milanpi_1.0.0.c
... and 40 more
Published
Feb 13, 2024
Tracked Since
Feb 18, 2026